View IRS21362DJPBF_3865005.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.irf.com 1 3-phase bridge driver packages description the irs2136xd (j&s) are high voltage, high speed power mosfet and igbt driver with three independent high side and low side referenced output channels for 3-phase applications. proprietary hvic technology enables ruggedized monolithic construction. logic inputs are compatible with cmos or lsttl outputs, down to 3.3 v logic. a current trip function which terminates all six outputs can be derived from an external current sense resistor. an enable function is available to terminate all six outputs simultaneously. an open-drain fault signal is provided to indicate that an overcurrent or undervoltage s hutdown has occurred. overcurrent fault conditions are cleared automatically after a delay programmed externally via an rc net work connected to the rcin input. the output drivers feature a h igh pulse current buffer stage designed for minimum driver cross-c onduction. propagation delays are ma tched to simplify use in high frequency applications. the floating channels can be used to drive n-channel power mosfets or igbts in the high side configuration which operates up to 600 v. part irs2136d irs21362d irs21363d irs2 1365d irs21366d irs21367d irs21368d input logic ___ ___ hin, lin ___ hin, lin ___ ___ hin, lin ___ ___ hin, lin ___ ___ hin, lin ___ ___ hin, lin ___ ___ hin, lin t on (typ.) 530 ns 530 ns 530 ns 530 ns 200 ns 200 ns 530 ns t off (typ.) 530 ns 530 ns 530 ns 530 ns 200 ns 200 ns 530 ns v ih (min.) 2.5 v 2.5 v 2.5 v 2.5 v 2.5 v 2.5 v 2.5 v v il (max.) 0.8 v 0.8 v 0.8 v 0.8 v 0.8 v 0.8 v 0.8 v v itrip+ 0.46 v 0.46 v 0.46 v 4.3 v 0.46 v 4.3 v 4.3 v v ccuv+ / v bsuv+ 8.9 v 10.4 v 11.1 v 11.1 v 11.1 v 11.1 v 8.9 v v ccuv- / v bsuv- 8.2 v 9.4 v 10.9 v 10.9 v 10.9 v 10.9 v 8.2 v features ? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transi ent voltage, dv/dt immune ? gate drive supply range from 10 v to 20 v (irs2136d/ irs21368d), 11.5 v to 20 v (irs21362d), or 12 v to 20 v (irs21363d/irs21365d/irs21366d/irs21367d ? undervoltage lockout for all channels ? over-current shutdown turns off all six drivers ? independent 3 half-bridge drivers ? matched propagation delay for all channels ? cross-conduction prevention logic ? integrated bootstrap diode function ? low side output out of phase wi th inputs. high side outputs out of phase (irs213(6,63, 65, 66, 67, 68)d), or in phase (irs21362d) with inputs ? 3.3 v logic compatible ? lower di/dt gate drive for better noise immunity ? externally programmable delay for automatic fault clear ? all parts are lead-free preliminary irs2136d/irs21362d/irs21363d/irs21365d/ irs21366d/irs21367d/irs21368d (j&s) pbf 28-lead soic 28-lead pdip 44-lead plcc w/o 12 leads applications: *motor control *air conditioners/ washing machines *general purpose inverters *micro/mini inverter drives data sheet no. pd60247revd feature comparison: irs2136xd typical connection
www.irf.com 2 irs213(6,62,63,65,66,67,68)d(j&s)pbf absolute maximum ratings absolute maximum ratings indicate sustained limits be yond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. zener clamps are included between v cc & com (25 v), v cc & v ss (20v), and v bx & v sx (20 v). recommended operating conditions the input/output logic-timing diagram is shown in fig. 1. for proper operation the device should be used within the recommended conditions. all voltage parameter s are absolute referenced to com. the v s & v ss offset ratings are tested with all supplies biased at a 15 v differential. symbol definition min. max. units irs213(6,68)d v s1,2,3 +10 v s1,2,3 + 20 irs21362d v s1,2,3 +11.5 v s1,2,3 + 20 v b1,2,3 high side floating supply voltage irs213(6,63,65,66,67)d v s1,2,3 +12 v s1,2,3 + 20 v s 1,2,3 high side floating supply voltage note 1 600 irs213(6,68)d 10 20 irs21362d 11.5 20 v cc low side supply voltage irs213(6,63,65,66,67)d 12 20 v ho 1,2,3 high side output voltage v s1,2,3 v b1,2,3 v lo1,2,3 low side output voltage 0 v cc v ss logic ground -5 5 v flt fault output voltage v ss v cc v rcin rcin input voltage v ss v cc v note 1: logic operational for v s of (com - 8 v) to (com + 600 v). logic state held for v s of (com - 8 v) to (com ? v bs ). (please refer to the design tip dt97-3 for more details). symbol definition min. max. units v s high side offset voltage v b 1,2,3 - 20 v b 1,2,3 + 0.3 v b high side floating supply voltage -0.3 625 v ho1,2,3 high side floating output voltage v s1,2,3 - 0.3 v b 1,2,3 + 0.3 v cc low side and logic fixed supply voltage -0.3 25 v ss logic ground v cc - 20 v cc + 0.3 v lo1,2,3 low side output voltage -0.3 v cc + 0.3 v in input voltage lin, hi n, itrip, en, rcin v ss -0.3 v cc + 0.3 v flt fault output voltage v ss -0.3 v cc + 0.3 v dv/dt allowable offset voltage slew rate ? 50 v/ns (28 lead pdip) ? 1.5 (28 lead soic) ? 1.6 p d package power dissipation @ t a +25 c (44 lead plcc) ? 2.0 w (28 lead pdip) ? 83 (28 lead soic) ? 78 rth ja thermal resistance, junction to ambient (44 lead plcc) ? 63 c/w t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c preliminary
www.irf.com 3 irs213(6,62,63,65,66,67,68)d(j&s)pbf recommended operating c onditions - (continued) the input/output logic-timing diagram is shown in fig. 1. for proper operation the device should be used within the recommended conditions. all voltage parameter s are absolute referenced to com. the v s & v ss offset ratings are tested with all supplies biased at a 15 v differential. symbol definition min. max. units v itrip itrip input voltage v ss v ss + 5 v in logic input voltage lin, hin (irs213(6,63,65,66,67,68)d), lin, hin (irs21362d), en v ss v ss + 5 v t a ambient temperature -40 125 c note 1: hin, lin, en and the itrip pin are internally clamped with a 5.2 v zener diode. static electrical characteristics v bias (v cc ,v bs1,2,3 ) = 15 v unless otherwise specified. the v in , v th , and i in parameters are referenced to v ss and are applicable to all six channels (hin1, 2,3/hin1,2,3 and lin1,2,3). the v o and i o parameters are referenced to com and v s1,2,3 and are applicable to the respective output leads: lo 1,2,3 and ho1,2,3. symbol definition min. typ. max. units test conditions logic ?0? input voltage lin1,2,3, hin1,2,3 irs213(6,63,65)d logic ?1? input voltage hin1,2,3 irs21362d 2.5 ? ? v ih logic ?0? input voltage lin1,2,3, hin1,2,3 irs213(66,67,68)d 2.5 ? ? logic ?1? input voltage lin1,2,3, hin1,2,3 irs213(6,63,65)d logic ?0? input voltage hin1,2,3 irs21362d v il logic ?0? input voltage lin1,2,3, hin1,2,3 irs213(66,67,68)d ? ? 0.8 v in , th+ input positive going threshold ? 1.9 ? v in , th- input negative going threshold ? 1 ? v en,th+ enable positive going threshold ? ? 2.5 v en,th- enable negative going threshold 0.8 ? ? v it,th+ (6,62,63,66) itri p positive going threshold 0.37 0.46 0.55 v it,hys (6,62,63,66) itrip hy steresis ? 0.07 ? v it,th+ (65,67,68) itrip positive goi ng threshold 3.85 4.3 4.75 v it,hys (65,67,68) itrip hy steresis ? 0.15 ? v rcin, th+ rcin positive going threshold ? 8 ? v rcin, hys rcin hysteresis ? 3 ? v oh high level output voltage, v bias - v o ? 0.9 1.4 v ol low level output voltage, v o ? 0.4 0.6 io = 20 ma v ccuv+ (6,68) v cc supply undervoltage positive going threshold 8 8.9 9.8 v ccuv- (6,68) v cc supply undervoltage negative going threshold 7.4 8.2 9 v ccuvhy (6,68) v cc supply undervoltage hysteresis 0.3 0.7 ? v bsuv+ (6,68) v bs supply undervoltage positive going threshold 8 8.9 9.8 v prelim i nary
www.irf.com 4 irs213(6,62,63,65,66,67,68)d(j&s)pbf static electrical charact eristics - (continued) v bias (v cc ,v bs1,2,3 ) = 15 v unless otherwise specified. the v in , v th , and i in parameters are referenced to v ss and are applicable to all six channels (hin1, 2,3/ hin1,2,3 and lin1,2,3). the v o and i o parameters are referenced to com and v s1,2,3 and are applicable to the respective output leads: lo 1,2,3 and ho1,2,3. symbol definition min. typ. max. units test conditions v bsuv- (6,68) v bs supply undervoltage negative going threshold 7.4 8.2 9 v bsuvhy (6,68) v bs supply undervoltage hysteresis 0.3 0.7 ? v ccuv+ (62) v cc supply undervoltage positive going threshold 9.6 10.4 11.2 v ccuv- (62) v cc supply undervoltage negative going threshold 8.6 9.4 10.2 v ccuvhy (62) v cc supply undervoltage hysteresis 0.5 1 ? v bsuv+ (62) v bs supply undervoltage positive going threshold 9.6 10.4 11.2 v bsuv- (62) v bs supply undervoltage negative going threshold 8.6 9.4 10.2 v bsuvhy (62) v bs supply undervoltage hysteresis 0.5 1 ? v ccuv+ (63,65,66,67) v cc supply undervoltage positive going threshold 10.4 11.1 11.6 v ccuv- (63,65,66,67) v cc supply undervoltage negative going threshold 10.2 10.9 11.4 v ccuvhy (63,65,66,67) v cc supply undervoltage hysteresis ? 0.2 ? v bsuv+ (63,65,66,67) v bs supply undervoltage positive going threshold 10.4 11.1 11.6 v bsuv- (63,65,66,67) v bs supply undervoltage negative going threshold 10.2 10.9 11.4 v bsuvhy (63,65,66,67) v bs supply undervoltage hysteresis ? 0.2 ? v i lk offset supply leakage current ? ? 50 v b =v s = 600 v i qbs quiescent v bs supply current ? 70 120 a i qcc quiescent v cc supply current ? 3 4 ma all inputs @ logic 0 value v in,clamp input clamp voltage (hin, lin, itrip and en) 4.8 5.2 5.65 v i in =100 a i lin+ (6,62,63,65) input bias cu rrent (lout = hi) ? 110 150 v in =4 v i lin- (6,62,63,65) input bias cu rrent (lout = lo) ? 150 200 v in =0 v i lin+ (66,67,68) input bias current (lout = hi) ? ? 3 v in =4 v i lin- (66,67,68) input bias cu rrent (lout = lo) ? ? 3 v in =0 v i hin+ (6,63,65) input bias current (hout = hi) ? 110 150 v in =4 v i hin- (6,63,65) input bias current (hout = lo) ? 150 200 v in =0 v i hin+ (62) input bias current (hout = hi) ? 5 20 v in =4 v i hin- (62) input bias current (hout = lo) ? ? 3 v in =0 v i hin+ (66,67,68) input bias current (hout = hi) ? ? 3 v in =4 v i hin- (66,67,68) input bias current (hout = lo) ? ? 3 v in =0 v i itrip+ ?high? itrip input bias current ? 5 40 v in =4 v i itrip- ?low? itrip input bias current ? ? 1 v in =0 v i en+ ?high? enable input bias current ? 5 40 v in =4 v i en- ?low? enable input bias current ? ? 1 a v in =0 v prelim i nary
www.irf.com 5 irs213(6,62,63,65,66,67,68)d(j&s)pbf static electrical charact eristics - (continued) v bias (v cc ,v bs1,2,3 ) = 15 v unless otherwise specified. the v in , v th , and i in parameters are referenced to v ss and are applicable to all six channels (hin1, 2,3/hin1,2,3 and lin1,2,3). the v o and i o parameters are referenced to com and v s1,2,3 and are applicable to the respective output leads: lo 1,2,3 and ho1,2,3. symbol definition min. typ. max. units test conditions i rcin rcin input bias current ? ? 1 a v rcin = 0 v or 15 v i o+ output high short circuit pulsed current 120 200 ? vo =0 v, pw ? 10 s i o- output low short circuit pulsed current 250 350 ? ma vo =15 v, pw ? 10 s r on_rcin rcin low on resistance ? 50 100 r on_fault fault low on resistance ? 50 100 i= 1.5 ma r bs internal bs diode r on ? 200 ? note 1: please refer to feature description section fo r integrated bootstrap f unctionality information. dynamic electrical characteristics dynamic electrical characteristics v cc = v bs = v bias = 15 v, v s1,2,3 = v ss = com, t a = 25 c and cl = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditions t on turn-on propagation delay 400 530 750 t off turn-off propagation delay 400 530 750 t on (66,67) turn-on propagation delay ? 200 ? t off (66,67) turn-off propagation delay ? 200 ? t r turn-on rise time ? 125 190 t f turn-off fall time ? 50 75 v in = 0 v & 5 v t en enable low to output shutdown propagation delay 350 460 650 t en (66,67) enable low to output shutdown propagation delay ? 300 ? v in, v en = 0 v or 5 v t itrip itrip to output shutdown propagation delay 500 750 1200 v itrip =5 v t bl itrip blanking time ? 400 ? t flt itrip to fault propagation delay 400 600 950 v in = 0 v or 5 v v itrip = 5 v t filin input filter time (hin, lin) (irs213(6,62,63,65,68)d only) 200 350 510 v in = 0 v & 5 v t filteren enable input filter time (irs213(6,62,63,65,68)d only) 100 200 ? dt deadtime 190 290 420 v in = 0 v & 5 v external dead time mt t on , t off matching time (on all six channels) ? ? 50 external dead time >420 ns mdt dt matching (hi->lo & lo->hi on all channels) ? ? 60 external dead time 0 s pm pulse width distortion (pwin-pwout) ? ? 75 ns pw input=10 s t fltclr fault clear time rcin: r = 2 m , c = 1 nf 1.3 1.65 2 ms v in = 0 v or 5 v v itrip = 0 v note 2: for high side pwm, hin pulse width must be ? 500 ns. prelim i nary
www.irf.com 6 irs213(6,62,63,65,66,67,68)d(j&s)pbf en itrip fault hin1,2,3 hin1,2,3 lin1,2,3 rcin ho1,2,3 lo1,2,3 fig. 1. input/output timing diagram 90% ten en 50% lin1,2,3 hin1,2,3 50% 50% 50% 50% pw in lin1,2,3 hin1,2,3 tr 10% ho1,2,3 lo1,2,3 90% tf ton toff 90% 10% ho1,2,3 lo1,2,3 pw out fig. 2. switching time waveforms fig. 3. output enable timing waveform prelim i nary
www.irf.com 7 irs213(6,62,63,65,66,67,68)d(j&s)pbf hin1,2,3 lin 1,2,3 50% 50% lin1,2,3 hin1,2,3 lo 1,2,3 ho 1,2,3 50% 50% 50% 50% dt 50% 50% dt fig. 4. internal deadtime timing waveforms rcin itrip fault any ouput titrip 50% 50% 90% tflt 50% tfltclr 50% fig. 5. itrip/rcin timing waveforms on off on hin/lin t in,fil low t in,fil n on off off high ho/lo fig. 6. input filter function preliminary
www.irf.com 8 irs213(6,62,63,65,66,67,68)d(j&s)pbf lead definitions symbol description v cc low side supply voltage v ss logic ground hin1,2,3 hin1,2,3 logic inputs for high side gate driver outputs (ho1,2,3), out of phase [irs213(6,63,65,66,67,68)d] logic inputs for high side gate driver outputs (ho1,2,3), in phase (irs21362d) lin1,2,3 logic input for low side gate driver outputs (lo1,2,3), out of phase fault indicates over-current (itrip) or low-side under voltage lockout has occurred. negative logic, open- drain output en logic input to enable i/o functionalit y. i/o logic functions when enable is high (i.e., positive logic) no effect on fault and not latched itrip analog input for overcurrent shutdown. when acti ve, itrip shuts down outputs and activates fault and rcin low. when itrip becomes inactive, fault stays active low for an externally set time t fltclr , then automatically becomes inactive (open-drain high impedance). rcin external rc network input used to define fault clear delay, t fltclr, approximately equal to r*c when rcin>8 v, the fault pin goes back into open-drain high-impedance com low side gate drivers return v b1,2,3 high side floating supply ho1,2,3 high side gate driver outputs v s1,2,3 high voltage floating supply return lo1,2,3 low side driver sourcing outputs note : lin, hin, en, and itrip are internally clamped with a 5.2 v zener diode. prelim i nary
www.irf.com 9 irs213(6,62,63,65,66,67,68)d(j&s)pbf lead assignments prelim i nary
www.irf.com 10 irs213(6,62,63,65,66,67,68)d(j&s)pbf functional block diagram prelim i nary
www.irf.com 11 irs213(6,62,63,65,66,67,68)d(j&s)pbf functional block diagram prelim i nary
www.irf.com 12 irs213(6,62,63,65,66,67,68)d(j&s)pbf functional block diagram prelim i nary
www.irf.com 13 irs213(6,62,63,65,66,67,68)d(j&s)pbf functional block diagram vcc vbs itrip enable fault lo1,2,3 ho1,2,3 v itrip 5 v 0 (note 3) 0 0 15 v 15 v 0 v 0 v high imp 0 0 note 1: a shoot-through prevention logic prevents lo1,2,3 and ho1, 2,3 for each channel from turning on simultaneously. note 2: uvcc is not latched, when v cc > uvcc, fault returns to high impedance. note 3: when v bs < uvbs, ho goes low. after v bs goes higher than uvbs, ho stays low until a new falling irs213(6,63,65,66,67, 68)d or rising irs21362d transition of hin. note 4: when itrip < v itrip , fault returns to high-impedance after rcin pin becomes greater than 8 v (@ v cc = 15 v). prelim i nary
www.irf.com 14 irs213(6,62,63,65,66,67,68)d(j&s)pbf 1 features description 1.1 integrated bootstrap functionality the irs2136xd family embeds an integrated bootstrap fet that allows an alternative drive of the bootstrap supply for a wide range of applications. there is one bootstrap fet for each channel and it is connected between each of the floating supply (v b1 , v b2 , v b3 ) and v cc (see fig. 7). the bootstrap fet of each c hannel follows the state of the respective low side output stage (i.e., bootfet is on when lo is high, it is off when lo is low), unless the v b voltage is higher than approximately 1.1(v cc ). in that case the bootstrap fet stays off until the v b voltage returns below that threshold (see fig. 8). fig. 7. simplified bootfet connection vcc=15v vth~17v lo bootfet on bootfet off bootfet on bootstrap fet state phase voltage fig. 8. state diagram bootstrap fet is suitable for most pwm modulation schemes and can be used either in parallel with the external bootstrap network (diode+resistor) or as a replacement of it. the use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations in the following situations: - when used in non-complementary pwm schemes (typically 6-step modulations) - at a very high pwm duty cycle due to the bootstrap fet equivalent resistance (r bs , see page 5). in these cases, better performances can be achieved by using the irs2136x non d version with an external bootstrap network. 2 pcb layout tips 2.1 distance from h to l voltage the irs2136xdj package lacks some pins (see page 8) in order to maximizing the distance between the high voltage and low voltage pins. it?s strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device (v b1,2,3 , v s1,2,3 ) side. 2.2 ground plane to minimize noise coupling ground plane must not be placed under or near the high voltage floating side. 2.3 gate drive loops current loops behave like an antenna able to receive and transmit em noise (see fig. 9). in order to reduce em coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector-to- gate parasitic capacitan ce. the parasitic auto- inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. fig. 9. antenna loops 2.4 supply capacitors supply capacitors must be placed as close as possible to the device pins (v cc and v ss for the ground tied supply, v b and v s for the floating supply) in order to minimize parasitic inductance/resistance. prelim i nary
www.irf.com 15 irs213(6,62,63,65,66,67,68)d(j&s)pbf 2.5 routing and placement power stage pcb parasitic may generate dangerous voltage transients for the gate driver and the control logic. in particular it?s recommended to limit phase voltage negative transients. in order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray in ductance. see dt04-4 at www.irf.com for more detai led information. prelim i nary
www.irf.com 16 irs213(6,62,63,65,66,67,68)d(j&s)pbf figures 10-30 provide information on the experimental performanc e of the irs2136ds hvic. the line plotted in each figure is generated from actual lab data. a large number of individual samples from multip le wafer lots were tested at three temperatures (-40 oc, 25 oc, and 125 oc) in order to generate the experimental (exp.) curve. t he line labeled exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. the individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on propagation delay (ns) exp . fig. 10. turn-on propagati on delay vs. temperature 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off propagation delay (ns ) exp . fig. 11. turn-off propagati on delay vs. temperature 0 75 150 225 300 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) exp . fig. 12. turn-on rise time vs. temperature 0 25 50 75 100 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) exp . fig. 13. turn-off fall time vs. temperature prelim i nary
www.irf.com 17 irs213(6,62,63,65,66,67,68)d(j&s)pbf 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) titrip propagation delay (ns) exp . fig. 14. dt propagatio n delay vs. temperature fig. 15. titrip propagatio n delay vs. temperature 0 200 400 600 800 1000 1200 -50 -25 0 25 50 75 100 125 temperature ( o c) itrip to fault propagation delay (ns) exp . fig. 16. itrip to fa ult propagation delay vs. tem p erature 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) ten sd propagation delay (ns) exp . fig. 17. ten sd propagati on delay vs. temperature 0 20 40 60 80 100 -50-250255075100125 temperature ( o c) rcin low on resistance ( ohm) exp . fig. 18. rcin low on re sistance vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( o c) fault low on resistance ( ohm) exp . fig. 19. fault low on resistance vs. temperature 0 150 300 450 600 -50 -25 0 25 50 75 100 125 temperature ( o c) dt propagation delay (ns) exp . prelim i nary
www.irf.com 18 irs213(6,62,63,65,66,67,68)d(j&s)pbf 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc quiescent current (ma) exp . fig. 20. v cc quiescent current vs. temperature 0 20 40 60 80 100 120 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs quiescent current (ua) exp . fig. 21. v bs quiescent current vs. temperature 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv+ threshold (v) exp . fig. 22. v ccuv+ threshold vs. temperature 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv- threshold (v) exp . fig. 23. v ccuv- threshold vs. temperature 5 6 7 8 9 10 -50-25 0 255075100125 temperature ( o c) v bsuv+ threshold (v) exp . fig. 24. v bsuv+ threshold vs. temperature 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 temperature ( o c) v bsuv+ threshold (v) exp . fig. 25. v bsuv- threshold vs. temperature prelim i nary
www.irf.com 19 irs213(6,62,63,65,66,67,68)d(j&s)pbf 0 200 400 600 800 -50 -25 0 25 50 75 100 125 temperature ( o c) i trip th- (mv) exp . fig. 26. i trip th+ vs. temperature fig. 27. i trip th- vs. temperature 200 400 600 800 -50-250255075100125 temperature ( o c) i trip th+ (mv) ex p. 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -50 -25 0 25 50 75 100 125 temperature ( o c) i o+ l1 sc pulsed currentt (a) exp . fig. 28. i o+ l1 sc pulsed current vs. temperature 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -50 -25 0 25 50 75 100 125 temperature ( o c) i o- l1 sc current (a) exp . fig. 29. i o- l1 sc pulsed current vs. temperature 0 4 8 12 16 -50-25 0 25 50 75100125 temperature ( o c) itrip input bias current (ua ) exp. fig. 30. itrip input bias current vs. temperature prelim i nary
www.irf.com 20 irs213(6,62,63,65,66,67,68)d(j&s)pbf case outlines prelim i nary
www.irf.com 21 irs213(6,62,63,65,66,67,68)d(j&s)pbf case outlines prelim i nary
www.irf.com 22 irs213(6,62,63,65,66,67,68)d(j&s)pbf carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c prelim i nary
www.irf.com 23 irs213(6,62,63,65,66,67,68)d(j&s)pbf order information worldwide headquarters: 233 kansas street, el segundo, ca 90245 tel: (310) 252-7105 this part has been qualified per in dustrial level http://www.irf.com data and specifications subject to change without notice. 5/19/2006 28-lead pdip irs2136dpbf 28-lead pdip irs21362dpbf 28-lead pdip irs21363dpbf 28-lead pdip irs21365dpbf 28-lead pdip irs21366dpbf 28-lead pdip irs21367dpbf 28-lead pdip irs21368dpbf 28-lead soic irs2136dspbf 28-lead soic irs21362dspbf 28-lead soic irs21363dspbf 28-lead soic irs21365dspbf 28-lead soic irs21366dspbf 28-lead soic irs21367dspbf 28-lead soic irs21368dspbf 44-lead plcc irs2136djpbf 44-lead plcc IRS21362DJPBF 44-lead plcc irs21363djpbf 44-lead plcc irs21365djpbf 44-lead plcc irs21366djpbf 44-lead plcc irs21367djpbf 44-lead plcc irs21368djpbf 28-lead soic tape & reel irs2136dstrpbf 28-lead soic tape & reel irs21362dstrpbf 28-lead soic tape & reel irs21363dstrpbf 28-lead soic tape & reel irs21365dstrpbf 28-lead soic tape & reel irs21366dstrpbf 28-lead soic tape & reel irs21367dstrpbf 28-lead soic tape & reel irs21368dstrpbf 44-lead plcc tape & reel irs2136djtrpbf 44-lead plcc tape & reel irs21362djtrpbf 44-lead plcc tape & reel irs21363djtrpbf 44-lead plcc tape & reel irs21365djtrpbf 44-lead plcc tape & reel irs21366djtrpbf 44-lead plcc tape & reel irs21367djtrpbf 44-lead plcc tape & reel irs21368djtrpbf prelim i nary

▲Up To Search▲

Price & Availability of IRS21362DJPBF

	To Download IRS21362DJPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .